System packaging platform

Glass-Based 3D Packaging

Glass-based 3D packaging replaces conventional silicon and organic interposers with a substrate that is electrically superior, mechanically stable, and scalable to panel-level production. At Zhongke Daojing, we have built a complete system-packaging line around Through-Glass Via (TGV) technology — from micro-via formation and metal filling through surface redistribution, wafer-level bonding, and final performance testing.

  • Complete process chain — via formation, metallization, multi-layer RDL, bonding, dicing, and test, all in-house.
  • Wafer and panel formats — 2″ to 12″ wafers and panels up to 510 × 510 mm.
  • Proven hermeticity — conductive-silicon TGV wafers with leak rates below 1 × 10⁻¹¹ Pa·m³/s.
One process recordFrom sampling to volume
Panel-compatibleUp to 510 × 510 mm
Data with each lotElectrical, mechanical, hermeticity
Cleanroom operator holding a large glass packaging panel
Panel-level glass substrate inspection for advanced packaging.

Glass-Based 3D Packaging by the Numbers

6
process steps: Via → Fill → RDL → Bond → Dice → Test, all in-house
<1×10⁻¹¹
Pa·m³/s helium leak rate on hermetic builds
2″–12″
Wafer sizes supported, plus panel up to 510 × 510 mm
3
bonding methods: laser welding · anodic · Au-Au thermocompression
Hourglass through-glass via geometry in a glass substrate
TGV via geometry: top, waist, bottom profile through glass.
Cross-section of through-glass vias in a glass substrate
Cross-section visual for TGV application discussion.

System Packaging Process

1

Via Formation & Filling

Sub-20μm through-glass vias formed by laser-induced etching, then filled by paste, electroplating, or resin-plug routes.
2

Surface Metallization & RDL

Single- and multi-layer redistribution on the TGV substrate surface, with ball placement for flip-chip or BGA interconnect.
3

Wafer-Level Bonding

Laser welding, anodic bonding, and gold-to-gold thermocompression qualified for high-reliability package assembly.
4

Dicing & Performance Test

Precision wafer dicing followed by electrical, mechanical, and hermeticity testing on every production lot.

Why Glass-Based 3D Packaging

The physics of glass make it a compelling alternative to silicon and organic interposers for advanced 3D integration. Glass is intrinsically insulating, so vertical interconnects carry signals with lower parasitic capacitance and lower dielectric loss than the same path through silicon — a decisive advantage in RF, millimeter-wave, and high-speed digital designs.

CTE matching across the stack

Glass CTE can be tuned to match both silicon dies above and organic PCBs below, reducing thermomechanical stress across the package.

Transparent, hermetic-capable substrate

Unlike silicon, glass is optically transparent, opening a path to photonic and sensor integration that opaque substrates cannot offer. It also supports wafer-level hermetic packaging.

Panel-level economics

Where silicon interposers are limited to round wafer formats, glass substrates can be fabricated on rectangular panels up to 510 × 510 mm, increasing the number of units per run and reducing cost per interposer.

Core Capabilities

Through-Glass Via (TGV)

Sub-20μm vias formed in batch across borosilicate, alkali-free, high-alumina silicate, and fused silica substrates. Positional tolerance held inside ±3μm.

Microvia Metal Filling

Four fill routes — low-temperature paste, high-temperature paste, electroplate-thicken with resin plug, and fully electroplated copper.

Surface Metallization & Multi-Layer RDL

Single- and multi-layer redistribution wiring on the TGV substrate, with solder ball placement for flip-chip or BGA interconnect.

Wafer-Level Bonding

Laser welding, anodic bonding, and Au-Au thermocompression for die attach, cap sealing, and hermetic packaging at wafer level.

Conductive-Silicon TGV

Glass high-temperature reflow recombines glass and silicon into a hybrid conductive-silicon TGV wafer for high-isolation and high-vacuum builds.

Testing & Verification

Electrical, mechanical, and hermeticity testing on every lot. Helium leak testing, bond-strength pull/shear, and full continuity data ship with each order.

Process Platform Overview

Platform Area In-House Capability
TGV formation Sub-20μm vias; vertical, tapered, and oblong profiles; 2″–12″ wafers and panels up to 510 × 510 mm
Metallization & filling Paste fill, electroplate-thickening with resin plug, and fully electroplated copper routes
RDL & bumping Single- and multi-layer redistribution wiring with solder ball placement for flip-chip or BGA interconnect
Bonding Laser welding, anodic bonding, and Au-Au thermocompression
Verification Electrical continuity, mechanical pull/shear, and helium leak testing with production data

Target Applications

For designs where high-density vertical interconnect, low-loss signal routing, and stable glass packaging determine device performance.
Through-glass via cross-section for MEMS and inertial sensor packaging

MEMS & Inertial Sensors

Hermetic, CTE-matched glass packaging for gyroscopes, accelerometers, and pressure sensors requiring vacuum or controlled-atmosphere cavities. Discuss application
Hourglass through-glass via structure for RF and millimeter-wave devices

RF & Millimeter-Wave Devices

Low-loss glass interposers that preserve signal integrity through dense vertical interconnect, replacing lossy silicon in filter, antenna, and front-end module packages. Discuss application
Large glass panel substrate for display, CPO, and neural interface packaging

Display, CPO & Brain-Computer Interfaces

High-density 3D integration on transparent glass substrates for co-packaged optics, Mini-LED backplanes, and next-generation neural interface arrays. Discuss application

Send Your Drawing for a Quote

Share your via geometry, substrate format, bonding requirements, and target test data. Our engineering team will review feasibility and DFM before sampling.
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